T4-2 PCIe physical slot layout

This is in response to a question I received in another blog post concerning the mapping of physical PCIe slots to the two controllers (and subsequentially CPUs). The answer (basically the table below) is big enough to justify it’s own blog post.

The T4-2 has 10 PCIe slots which are serviced by two PICe controllers, one for each CPU. Knowing which slot belongs to which controller is useful to optimize performance throughput and also for some Oracle VM for Sparc setups where you may decide to map a whole PCIe bus or a single device to a certain logical domain (LDom).
When you stand behind the server, these slots are easily numbered 0 to 9 from left to right. In between, there is also one extra network module slot dedicated for a 10GbE module which won’t accept normal PCIe cards. All slots accept physical x8 connectors, two of them also support x16. And two of the slots are only wired for x4 speeds so avoid these for adapters that support x8 and need the throughput.

physical slot Controller Physical Electrical
0 pci_0 x8 x8
1 pci_1 x8 x8
2 pci_0 x8 x8
3 pci_0 x16 x8
4 pci_0 x8 x4
5 pci_0 x8 x4
6 pci_1 x16 x8
7 pci_1 x8 x8
8 pci_1 x8 x8
9 pci_1 x8 x8

The release notes also mention some additional rules and restriction on the use of certain cards in some of the slots for cooling requirements.

3 thoughts on “T4-2 PCIe physical slot layout

  1. Is there a similar table for the T5-2 & T5-4 servers?
    Also where do you get this information from ? :)

  2. Please refer to MOS document number 1005907.1 as the diagram in the PDF above and the table above are both incorrect.
    pci_0 owns: Slots 0, 2, 4, 6, 8
    pci_1 owns: Slots 1, 3, 5, 6, 9

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